This invention relates to a high-level programming language compiler, and more particularly, this invention relates to a high-level programming language compiler that converts a high-level programming language into hardware constructs.
Programmable logic provides may benefits in the design and manufacture of hardware and software systems. For example, efficiencies with respect to cost and time are known benefits. Programmable logic allows designers to avoid having to hard-wire circuits. Designers typically use specialized hardware design software to create logic circuits by interconnecting various types of logic gates, memory, etc on a computer screen.
Some known software packages allow the designer to write code in which various hardware constructs are specified. These software packages are typically specially designed for use with particular programmable logic hardware.
These tools do not, however, reach the ease of use and range of compatibility as do high-level language software compilers. For example, JAVA and C++ are widely used high-level languages that can be used to create various types of software constructs, such as loops, conditionals, functions, etc. with ease. These software constructs are compiled into a software program that can be executed on a computer's microprocessor (i.e., using the built-in instruction set). There does not exist any such high-level language compiler that can compile pure software constructs (i.e., that are transparent with regard to hardware) into programmable logic configuration data.
Moreover, the tools that are available for generating programmable logic in hardware typically lack the ability to produce efficient circuitry. For example, most of these tools implement software variables as registers in hardware. This leads to the necessity of having to multiplex every write to a register. Because multiplexers are large and slow in programmable logic, this implementation inherently leads to inefficiencies and makes retiming the circuit difficult.
One of the advantages of using hardware over software implementations is that hardware offers a greater degree of parallelism than does software. Software constructs typically execute in a sequential order. For example, loop iterations execute one after the other and conditional statements are evaluated before deciding whether to execute an ELSE construct or a THEN construct. The parallel nature of hardware has the potential to provide for more efficient execution and decision-making than that offered by software. However, present-day programmable logic compilers and tools do not generate programmable logic that takes full advantage of its parallel nature.
It would therefore be desirable to have a software-to-hardware compiler that maps pure software constructs into hardware constructs implemented in programmable logic.
It would further be desirable to be able to generate hardware in programmable logic that is optimized for parallelism.